Digital frequency synthesisers are commonly used for synthesising a swept frequency output signal waveform, the frequency of which is stepped through a plurality of frequencies in order to produce a frequency sweep. A typical prior art digital frequency synthesiser is illustrated in FIG. 1, and is indicated generally by the reference numeral 100. The prior art digital frequency synthesiser 100 comprises a direct digital frequency synthesiser 101 which produces the frequency swept synthesised output signal on an output terminal 102. The direct digital synthesiser 101 comprises a numerical controlled oscillator (not shown) which is clocked by a system clock, and sequentially produces digital data words indicative of the phase of an output signal to be synthesised in response to a frequency control digital word applied to a frequency control input 104 of the direct digital synthesiser 101. A digital signal processing circuit (also not shown) in the direct digital synthesiser 101 converts the digital data words from the numerical controlled oscillator (not shown) into phase dependent magnitude digital words, which are in turn converted to the synthesised output signal waveform in a digital-to-analogue converter (not shown) also in the direct digital synthesiser 101, and the synthesised output signal is produced on the output terminal 102. By periodically and appropriately altering the value of the frequency control digital word applied to the frequency control input 104, the frequency of the synthesised output signal produced on the output terminal 102 is correspondingly altered for sweeping the frequency of the synthesised output signal through a frequency sweep. The system clock signal is typically externally derived, and is applied to a system clock input terminal 105 of the digital frequency synthesiser 100, and in turn is applied to a clock input 106 of the direct digital synthesiser 101. Typically, a numerical controlled oscillator comprises a modulo-M accumulator which repeatedly accumulates each value of the frequency control digital word as the values of the frequency control digital words are sequentially applied to the frequency control input 104. A reset input 108 of the direct digital synthesiser 101 is provided for applying a reset signal for resetting the numerical controlled oscillator and the digital signal processing circuit of the direct digital synthesiser 101.
The values of the frequency control digital word and the rate at which, and the sequence in which, the values of the frequency control digital word are to be applied to the frequency control input 104 of the direct digital synthesiser 101 is determined externally, for example, by a computer, or as illustrated in FIG. 1 by a microcontroller 110. The digital frequency synthesiser 100 comprises a pair of addressable frequency control digital word storing registers 112 for alternately storing the current value of the frequency control digital word to be applied to the frequency control input 104 of the direct digital synthesiser 101 and the next value thereof. The values of the frequency control digital word determined by the microcontroller 110 are applied to the frequency control digital word storing registers 112 in the appropriate sequence by the microcontroller 110 through a serial communication port 115 and an asynchronous digital interface circuit 114 of the digital frequency synthesiser 100. Alternate values of the frequency control digital word are written to the respective frequency control digital word storing registers 112 so that the current and next values of the frequency control digital word are alternately stored in one of the frequency control digital word storing registers 112, and the next and current values of the frequency control digital word are alternately stored in the other of the frequency control digital word storing registers 112. Accordingly, while the current value of the frequency control digital word is being applied to the frequency control input 104 of the direct digital synthesiser 101 from one of the frequency control digital word storing registers 112, the next value of the frequency control digital word is being written to the other of the frequency control digital word storing registers 112.
A multiplexer 116 of the digital frequency synthesiser 100 is operated under the control of the microcontroller 110 for selectively and alternately applying the values of the frequency control digital word stored in the respective frequency control digital word storing registers 112 to the frequency control input 104 of the direct digital synthesiser 101. A timing signal applied by the microcontroller 110 to the multiplexer 116 through a terminal 118 of the digital frequency synthesiser 100 operates the multiplexer 116 for selectively and alternately applying the values of the frequency control digital word stored in the frequency control digital word storing registers 112. A reset signal from the microcontroller 110 is applied to the reset input 108 of the direct digital synthesiser 101 through a terminal 120 of the digital frequency synthesiser 100 for resetting the direct digital synthesiser 100.
The output frequency of the synthesised output signal produced on the output terminal 102 can be represented by the following equation:
      f    out    =            FCD      MOD        ·          f      s      where                fout is the frequency of the synthesised output signal,        fs is the frequency of the system clock signal applied to the system clock input terminal 105 at which the direct digital synthesiser 101, and in turn the accumulator is clocked,        FCD is the value of the frequency control digital word applied to the accumulator, and        MOD is the value of the modulus M of the accumulator.        
In order to produce a frequency swept synthesised output signal with a predefined frequency sweep, the frequency sweep must be defined in the frequency domain and in the time domain. In general, the synthesised frequency output signal is swept through a sequence of frequencies in ascending or descending order of frequencies, and in general, in an ascending order of frequencies. Thus, where the sequence of frequencies through which the synthesised output signal is to be swept is an ascending order of frequencies, in general, the frequency domain is defined by the start frequency, which is the lowest frequency of the frequency sweep and the end frequency, which is the highest frequency of the frequency sweep, and the number of frequencies through which the frequency is to be stepped. The time domain of the frequency sweep is defined by the duration of each frequency step, in other words, the time interval between two consecutive changes in the frequency of the synthesised output signal. In cases where the frequency swept synthesised output signal is to be provided with bursts of the frequencies during respective frequency steps of the frequency sweep, the duration of each frequency burst within the duration of each frequency step must also be defined as part of the time domain of the frequency sweep. Thus, in the digital frequency synthesiser 100 data defining the frequency sweep in the frequency domain is written to the data registers 112 through the interface circuit 114, and data defining the frequency sweep in the time domain is provided by the microcontroller 110 through the timing terminal 118. Other arrangements for providing data defining the frequency and time domains of the frequency sweep of a desired frequency swept synthesised output signal to a digital frequency synthesiser will be known to those skilled in the art.
In general, it is desirable that the frequency sweep of a frequency swept synthesised output signal produced by a digital frequency synthesiser should be produced with a predefined relationship with respect to time. For example, in many cases it is desirable that the frequency sweep produced by a digital frequency synthesiser should be produced with a predefined linear relationship with respect to time with the durations of the respective frequency steps being constant. Such a frequency sweep is produced by applying the values of the frequency control digital word to the frequency control input of the direct digital synthesiser at a constant rate. In general, in digital frequency synthesisers known heretofore, it is difficult to achieve linearity of the frequency sweep with respect to time, since the values of the frequency control digital word are not always provided on time to the digital frequency synthesiser, or where the values of the frequency control digital words are provided on time, they are not always applied on time to the direct digital synthesiser. This is due to the fact that the values of the frequency control digital word are computed and applied to the direct digital synthesiser by external devices, such as, as described with reference to FIG. 1, where the values of the frequency control digital word are computed by the microcontroller 110, and are applied to the frequency control input 104 of the direct digital synthesiser 101 under the control of the microcontroller 110. In general, such devices carry out other functions and tasks, as a result of which delays in applying the next value of the frequency control digital word may occur. In which case, the predefined relationship of the frequency sweep with respect to time no longer exists. This is undesirable.
The present invention is directed towards providing a digital frequency synthesiser and a method for producing a frequency swept synthesised frequency output signal, the frequency of which is swept through a plurality of frequencies of a frequency sweep with a predefined time relationship.